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TH7301
Dual-Channel Programmable Low-Pass Filter
Description
The device incorporates two matching 4th-order Butterworth filters with voltage gain control to perform low-pass filtering on quadrature demodulated signals. The cutoff frequency and inband gain are programmable via a standard 3-wire interface. The cutoff frequency can be set between 0.8 MHz and 22.4 MHz and the inband voltage gain can be set between -3 dB and 20 dB. The cutoff frequency value is determined via a 10-bit control word, with smaller step sizes in the lower portion of the cutoff frequency range. The device contains an on-chip oscillator to adjust the cutoff frequency. Maintaining amplifiers configure the Butterworth filter as the phase shift component of the oscillator. The frequency of oscillation tracks the filter cutoff frequency. The cutoff frequency of the filter can be accurately set according to the resolution of the IC by measuring the frequency of oscillation.
Features
Y Wide cutoff frequency range (0.8 MHz to Y Y
22.4 MHz) Dual-channel architecture produces superior matching and ease of use for quadrature signals Companding design provides higher resolution at lower cutoff frequencies
Y Low power consumption (<105 mA, typical 55 mA Y Single ended or differential input operation Y No external components for trimming necessary Y Small package (16-pin SOP)
possible (AC coupled) from -5 V supply; Fc = 1 MHz @ 25C)
Applications
Y Digital Broadcasting Systems (DBS) and Y Y
Digital Video Broadcasting (DVB) Satellite and cable TV decoders Microwave point to point links
Block Diagram
Fixed Gain 4th Order Butterworth Filter
4th Order Butterworth Filter Fixed Gain
Figure 1: Block Diagram
Rev. 2.1 November 1999
TH7301 Dual-Channel Programmable Low-Pass Filter
Theory of Operation
The IC is divided into I and Q channel signal paths each consisting of an input stage, gyrator 4th order Butterworth low-pass filter, output stage and feedback amplifier for an oscillator. A serial interface is provided to allow the gain and cutoff frequency to be programmed via a standard 3 wire interface. The digital cutoff frequency setting is converted to a current by a digital-to-analog converter. Internal bandgap references and biasing blocks provide top level biasing on voltage and current references for the complete device. Input stage The device incorporates programmable attenuation in the input stages to maintain filter linearity and to provide overall gain control for the IC. The attenuation can be programmed in coarse steps of 3 dB with fine control of 0.5 dB in the input transconductor of the gyrator filters. Internal multiplexers and back to back followers allow single-ended or differential input operation on both I and Q signal paths. 4th order Butterworth filter The filter architecture is based on a fully balanced continuous time gyrator technique with 4th order Butterworth response. Linear current programmable transconductance elements are used to synthesise the two inductors and source and termination impedance of the filter. A termination to source impedance ratio of 2:1 is selected to minimise output noise while maintaining a realisable range of capacitor values. The use of a differential architecture has three distinct advantages. Firstly the ultimate noise rejection is substantially better than that of the unbalanced LC filter. Secondly differential drive allows the use of a current programmable Gm stage with very much greater signal handling. And finally DC loading of the output is common mode and does not lead to differential DC offsets. This last point is especially important as the bias current within the filter can become very low at low cutoff frequencies. Output stage The output stage is designed to carry out differential to single ended conversion and provides the capability of driving up to 15 pF of capacitive load.
Oscillator The maintaining and limiting amplifier is used as part of a phase shift oscillator circuit with the gyrator Butterworth filter as the phase shift element. The frequency of oscillation occurs at the -3 dB frequency of the filter as the phase shift through a 4th order Butterworth filter is 180 degrees at the -3 dB point. Voltage limiters are integrated into the gyrator filters and limit the differential voltage to 50 mVpp in order to ensure that the transconductance elements remain in their linear region of operation and hence the expected inductance values are synthesised. Serial interface The filter cutoff frequency and gain are programmed via a 3 wire serial interface bus. The interface consists of the serial data clock (SCLK), serial data input (SDATA) and a serial enable (SDEN). The filter is programmed by asserting SDEN and clocking the 8 bit serial data, MSB first, into the shift register. The two most significant bits represent the register address bits. The 6 LSB of data are loaded into the relevant register on the falling edge of SDEN. The serial interface consists of: an 8 bit serial input to parallel output (SIPO) register, three 6-bit parallel load registers and register address decode logic. Once SDEN is asserted, data is clocked into the SIPO on the positive edge of SCLK. When the data is loaded, the two address bits are decoded to determine which register should be updated. The data is transfered to the register on the falling edge of SDEN. The serial interface does not contain a power on reset, thus all three registers must be programmed before reliable filter operation can be achieved. DAC The digital-to-analog converter is used to select the filter cutoff frequency via a programmable reference current. The fully companding DAC divides the frequency range into 5 chords, each with 128 equal frequency steps. The reference current is programmed by an external resistor placed between RDAC and Vee. The final output is mirrored for the I and Q channels to provide isolation. The chords are selected by a 3 bit word and the frequency step by a 7 bit word. The companding law is generated by adding the chord currents and dividing the required chord into 128 step currents.
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TH7301 Dual-Channel Programmable Low-Pass Filter
Pinout Information
The TH7301 is contained in a plastic 16 pin SOP package.
Figure 2: Pinout Schematic
Pin Definition List
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol VCCI IIN IREF VDD VSS QREF QIN VCCQ QOUT VEEQ RDAC SDEN SCLK SDATA VEEI IOUT
Function I channel positive supply I channel signal input I channel signal reference Digital positive supply Digital negative supply Q channel signal reference Q channel signal input Q channel positive supply Q channel output Q channel negative supply DAC reference current setting resistor connects between this pin and negative rail Serial data enable Serial data clock Serial data input I channel negative supply I channel output
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TH7301 Dual-Channel Programmable Low-Pass Filter
Serial Interface Programming
The serial interface is a 3-wire bus used to program the filter cutoff frequency and voltage gain. Pin SDATA is the serial data input for an 8bit shift register, SCLK is the shift register clock (active positive edge), SDEN (active high) is the serial interface enable. Note that logic levels are
referenced to a - 5 V supply and that there is no global reset for the logic devices, so a reset word should be input after power up. The timing diagram for the interface is shown below.
Figure 3: Serial Interface Timing Diagram
Operating conditions for the 3 wire interface
Parameter Power supply voltage High level input voltage Low level input voltage Serial data clock period Serial data setup time Serial data hold time Serial data enable delay time Serial data enable hold time Notes:
Symbol VSS VIH VIL tCLK tSD tHD tDEN tHEN
Min -5.25 0.3 * VSS VSS - 0.1V 50 10 10 20 20
Typ -5.0
Max -4.75 VDD + 0.1V 0.7 * VSS
Unit V
Comments relative to VDD note note
ns ns ns ns ns
Logic threshold levels for inputs SCLK, SDATA and SDEN. Note that this is a negative supply IC.
The serial data is stored in one of 3 internal registers - gain control, frequency select A and frequency select B. The first two bits of the serial data form an address code for the registers. The gain control bits AC(5...0) are decoded to select a voltage gain between 0 dB and 20.5 dB in 0.5 dB steps. The frequency select bits FC(2...0) select one of the octave chords while FS(6...0) select the step within each chord.
Address Bits Usage D7 Frequency Select A Frequency Select B Gain Control 0 0 1 D6 0 1 1
Additional bit OS0 (active high) controls the oscillator (for test issues only). The table below shows the address and data decoding of the serial data input. The serial interface does not contain a power on reset, thus all three registers must be programmed after power on to prevent undefined logical states and to achieve reliable filter operation. I. e. a first reset word may reset all registers to 0.
Data Bits D5 FS2 OS0 AC5 D4 FS1 0 AC4 D3 FS0 FS6 AC3 D2 FC2 FS5 AC2 D1 FC1 FS4 AC1 D0 FC0 FS3 AC0
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TH7301 Dual-Channel Programmable Low-Pass Filter
Definition of Terms
fcset fc fstep Av
-
cutoff frequency setting cutoff frequency (-3dB bandwidth) step size voltage gain The tables below show the selectable frequency settings.
FC (2..0) 000 001 010 011 1xx Frequency range fmin ... fmax (MHz) 0.8 ... 1.5937 1.6 ... 3.1875 3.2 ... 6.375 6.4 ... 12.75 12.8 ... 25.5 Step size fstep (kHz) 6.25 12.5 25 50 100
Frequency Setting
To maintain frequency resolution at low frequencies a companding law is applied to the frequency code. The frequency range is selected as one of the five octaves in the total filter range controlled by bits FC(2...0). Each octave is divided linearly into 128 equally sized steps decoded by bits FS(6...0). This frequency range is for an external resistor value of 4.5 k between pin RDAC and VEE. The range is designed to guarantee 0.8 MHz to 22.4 MHz cutoff range, taking process variations in top account without the need to change this external resistor. If there is a need to fine tune this frequency range for any reason, it may be re-centered by selecting a suitably valued external resistor.
The 128 steps within each octave are decoded by FS(6...0). The according control mechanism applies identically to all octaves refering to the appropriate step sizes of each octave, as shown in the tables and the example below. Example: FC(2...0) = 000 (frequency range 0.8 ... 1.5937 MHz, Step size = 6.25 kHz) FS(6...0) = 0000011 fcset = 0.81875 MHz
FS (6...0) 0000000 0000001 0000010 0000011
. . .
Step N 0 1 2 3
. . .
Cutoff Frequency fcset = fmin + N*fstep (MHz) fcset = fmin fcset = fmin + fstep fcset = fmin + 2*fstep fcset = fmin + 3*fstep
. . .
1111111
127
fcset = fmin + 127*fstep
Gain Setting
The gain control bits AC(5...0) are decoded to select a voltage gain between -3 dB and 20.5 dB in 0.5 dB steps. The gain control is divided into 8 steps controlled by AC(2...0) with additive step sizes of 0.5 dB decoded by AC(5...3). For example, to set the gain to 16 dB AC(5...0) = 011001. The table below shows the gain setting.
AC(2...0) 000 001 010 011 100 101 110 111
Gain (dB) 18 15 12 9 6 3 0 -3
AC(5...3) 000 001 010 011 100 101 110 111
Gain (dB) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.0
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TH7301 Dual-Channel Programmable Low-Pass Filter
Operating Characteristics
Absolute Maximum Ratings
Parameter Power supply voltage Input voltage - logic inputs Junction temperature Storage temperature Notes: Symbol VEE, VSS Vi Tj Tstg Min -7 VSS - 0.3V -40 -40 Typ Max 0.3 0.3V +150 +125 C C Unit V Conditions
All voltages relative to VCC, VDD
Operating Conditions
Parameter Power supply voltage Operating temperature range Notes: Symbol VEE, VSS Top Min -5.25 0 Typ -5.0 Max -4.75 70 Unit V C Conditions relative to VCC, VDD
The device has been designed for a negative supply system. It can be also used for positive supply systems if the input signals are referred to VCC, VDD.
DC Characteristics These characteristics are guaranteed for all settings of cutoff frequency and gain(unless otherwise stated). The value of the external DAC resistor is RDAC = 4.5 k.
Parameter Symbol Test level Min.value Typ.value Max.value Unit Conditions
Digital Supply Current Analog Supply Current (I + Q Channel) Analog Supply Current (I + Q Channel) at High Temperature DC Input Voltage DC Output Voltage High Level Input Voltage Low Level Input Voltage
Iss Iee Iee
1 1 3
-5 -60 -92
mA mA fcset = 0.8 MHz; 25 C mA fcset = 22.4 MHz; 70 C
Vi,DC Vo,DC VIH VIL
1 2 1 1 -3.2V 0.3*VSS VSS 0.1V
-0.8 -2.5 -1.9 VDD +0.1V 0.7*VSS
V V
internal bias voltage
Av = 20.5 dB gain setting
see note 1 see note 1
AC Characteristics These characteristics are guaranteed for cutoff frequency settings fcset = 0.8 ... 22.4 MHz (unless otherwise stated). The value of the external DAC resistor is RDAC = 4.5 k.
Parameter Symbol Testlevel Min. Typ. Max. Unit Conditions
Initial Cutoff Frequency Accuracy Frequency Cutoff Resolution Accuracy Passband Amplitude Peaking Stopband Attenuation 1 Stopband Attenuation 2
fcacc fcmon Apass A attn1 A attn2
2 3 3 3 3
-15 -25 -3.0 -0.5 12 50
+25 +10 3.0 0.5 14 65
% % % dB dB dB
fcset 6.375 MHz fcset 6.4 MHz referenced to f c monotonicity guaranteed 10 Hz f 0.5fc see figure 7 @ f = 1.5fc 5fc < f < 200 MHz +
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TH7301 Dual-Channel Programmable Low-Pass Filter
Operating Characteristics (continued)
Parameter
Symbol
Test level
Min.
Typ.
Max.
Unit
Conditions
Passband Group Delay Ripple Initial Gain Accuracy Gain Step Accuracy (monotonicity guaranteed) Output Signal-to-Noise Ratio Crosstalk between Channels Gain Match between Channels Bandwidth Match between Channels Passband Group Delay Match between Channels Total Harmonic Distortion Power Supply Rejection Intermodulation Distortion Output Voltage Input Resistance Input Capacitance Load Resistance Load Capacitance
Notes
tpass A vacc Avmon SNR Xtalk Avmatch fcmatch tpassm THD PSR IMD Vo R in Cin R ld C ld
3 2 3 3 3 2 2 3 5 4 3 3 4 4 4 4
6 -2.5 - 1.0 37 40 - 0.8 -10 -5 -3 1.0 40 - 48 38 50
12 3.0 1.0
ns dB dB dB dB
10 Hz f 0.5fc see note 2, 3 and figure 8 see note 4 and figures 9 and 10
see note 5 see note 6, 7
0.8 10 5 +3 2.5
dB % % ns % dB fcset 6.375 MHz fcset 6.4 MHz 10 Hz f 0.5fc see note 8 see note 9 see note 10
- 37 1.0
dBc
VPP see note 11 k pF k see note 12
3.0 12 1 15
pF
1. Logic threshold levels for inputs SCLK, SDATA and SDEN. Note that this is a negative-supply device (VEE,VSS = -5 V, VCC, VDD = 0 V). It can be also used for positive-supply systems if the input signals are referred to VCC, VDD = +5 V and VEE,VSS = 0 V. 2. fcset = 10 MHz, Av = 10 dB 3. passband group delay ripple for an ideal 4 pole Butterworth under the same conditions is 6ns 4. measured at 0.25fc 5. V o = 1 VPP, measured within the filter's noise bandwidth, f cset = 10 MHz, Av = 10 dB, fin < fc 6. Vo = 1 VPP, for Xtalk IQ I driven Q measured, Xtalk QI Q driven I measured, f cset = 22.4 MHz, Av = 20.5 dB, 7. fin = 5 MHz 8. fin = 0.25fc ; Vo = 1 VPP; C ld = 15 pF, A v = 10 dB 9. 100mVPP from 10 Hz to 1 MHz on VEE,VSS referred to the output. 10. fcset = 10 MHz, Av = 10 dB; tones at f1= 15 MHz and f2 = 25 MHz with 300 mVPP each 11. R ld = 1 k, for linear gain and not to exceed Xtalk, THD and IMD 12. AC coupled or DC coupled to VEE, VSS
Test levels (DC and AC Characteristics) level 1: level 2: level 3: level 4: level 5: production tested at 25 C and over full power supply range production tested at 25 C and VEE = -5.0 V guaranteed by design and characterization test over full temperature and power supply range typical value only, not confirmed by test guaranteed by design and characterization at 25 C and VEE = -5.0 V
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TH7301 Dual-Channel Programmable Low-Pass Filter
Application Diagram
The application diagram below is an example diagram and provided to assist the customer in
using the IC. The configuration can be changed for other applications.
I channel Output
1
VCCI IIN IREF VDD
IOUT VEEI SDATA SCLK
16 15
I channel Input C2 C1
2 3 4
C6
14 13 12
-5 Vdc
5
TH7301
VSS QREF QIN VCCQ SDEN RDAC VEEQ QOUT C5
6 11 10 9
3-wire Serial Interface RDAC
-5 Vdc
C4 Q channel Input
7
C3
8
C7 Q channel Output
Figure 4: Application Diagram
Component List for Application Diagram
The AC coupling capacitors (C1-C4) will produce a high pass pole with the 3k input resistance. Their value should be chosen such that this pole is below any frequencies of interest in the system.
Component Function
The Rdac resistor is the current setting resistor for the DAC. The recommended values are listed below.
Value
Unit
C1, C2, C3, C4 C5, C6, C7 RDAC
AC coupling capacitors AC coupling capacitors DAC current setting resistor
100 22 4.5
nF nF k
Important notice
It is recommended to operate the device from a single power supply for both analog and digital sections of the device. Operation from separate power supplies on VEE and VSS and absence of the digital voltage may cause destruction of the device. The serial interface does not contain a power on reset, thus all three registers must be programmed after power on to prevent undefined logical states and to achieve reliable filter operation. I. e. a first reset word may reset all registers to 0.
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TH7301 Dual-Channel Programmable Low-Pass Filter
Filter Characteristics
The following diagrams illustrate some of the main functions and characteristics of the programmable low-pass filter. They represent evaluation results on the existing silicon.
Av = 10 dB typ max
100 * (fci- fcset)/fcset
min
fcset [MHz]
Figure 5: Measured cutoff frequency accuracy vs. settings (VEE = -5.00 V / Ta = 25C)
typ typ
100 * (foi- fcset)/fcset
max max min min
fcset [MHz]
Figure 6: Measured oscillator frequency deviation vs. settings (VEE = -5.00 V / Ta = 25C)
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TH7301 Dual-Channel Programmable Low-Pass Filter
Filter Characteristics (continued)
Figure 7: amplitude response (Av = 10 dB, fcset = 10 MHz, VEE= -5.0 V, Ta = 23 C)
Figure 8: passband group delay ripple (Av = 10 dB, fcset = 10 MHz, VEE = -5.0 V, Ta = 23 C)
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TH7301 Dual-Channel Programmable Low-Pass Filter
Filter Characteristics (continued)
Figure 9: initial gain accuracy (fcset = 0.8 MHz, fmeas = 0.2 MHz, VEE = -5.0 V, Ta = 23 C)
Figure 10: initial gain accuracy (fcset = 22.4 MHz, fmeas = 5.0 MHz, VEE = -5.0 V, Ta = 23 C)
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TH7301 Dual-Channel Programmable Low-Pass Filter
Package Information
The device is available in SOP WB 16 package.
Small Outline Package (SOP) SOP 16 Wide Body (WB) Package type SOP WB 16 min max D 0.398 0.413 E 0.283 0.300 H 0.393 0.419 A 0.091 0.111 A1 0.002 0.014 e 0.05 b 0.013 0.020 L 0.012 0.050 Package code DF16
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Dimensions in inches, coplanarity < 0.004", original dimension: inch
Small Outline Package (SOP) SOP 16 Wide Body (WB) Package type SOP WB 16 min max D 10.11 10.49 E 7.19 7.62 H 9.98 10.64 A 2.31 2.82 A1 0.05 0.36 e 1.27 b 0.33 0.51 L 0.30 1.27 Package code DF16
10
Dimensions in millimeters, coplanarity < 0.1 mm, original dimension: inch
Ordering Information
The TH7301 Programmable Low-Pass Filter IC is available in a 16 pin SOP WB package and for the Operating Temperature range of 0 C...+70 C (Commercial). The order number is TH7301C (C=Commercial).
Quality Data
Quality data is available on request. Contact:
Thesys Gesellschaft fur Mikroelektronik mbH Quality Assurance Haarbergstr. 67, 99097 Erfurt, Germany Tel.: +49-361-4276155, Fax: +49-361-4276060
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TH7301 Dual-Channel Programmable Low-Pass Filter
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TH7301 Dual-Channel Programmable Low-Pass Filter
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E-Mail: info@thesys.de http:// www.thesys.de
Thesys Sales Offices
n Germany
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Important Notice
Devices sold by Thesys are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Thesys makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Thesys reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Thesys for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Thesys for each application. The information furnished by Thesys is believed to be correct and accurate. However, Thesys shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Thesys rendering of technical or other services. (c) 1997 Thesys Gesellschaft fur Mikroelektronik mbH. All rights reserved.
This data sheet is printed on environmentally friendly paper, bleached without chlorine.
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10LT.053E

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